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  • Magic VLSI  v.7.3.91"Magic" VLSI layout tool and various incarnations of the Berkeley ...
  • VLSI Layout 3D  v.1.0VLSI Layout 3d is a 3d visualization software for VLSI designs created in LASI. This project is gearing up to go open-source!
  • VLSI Library  v.1.0This project aims to create and distribute a full featured VLSI library under free licenses in order to contribute to the open hardware community and to the progress of peoples.
  • Alliance CAD System  v.1.0Alliance CAD System is a free set of EDA tools and portable cell libraries for VLSI design. It covers the design flow from VHDL up to layout. It includes VHDL simulator, RTL synthesis, place and route, netlist extractor, DRC, layout ...
  • Linux driver for CPiA webcams  v.1.3.1We provide Linux drivers for webcams based on the popular Vision VLSI CPiA chipset, including the Creative WebCam II. Both parport and USB is ...
  • The PPPP Program  v.04PPPP is a computer program used for partitioning parameterized orthogonal polygons into parameterized rectangles. With this program, it is possible to build rectangular corner stitching data structure for parameterized VLSI ...
  • BookSim  v.1.0A cycle-accurate interconnection network simulator. Brought to you by the Concurrent VLSI Architecture group at Stanford University. The SourceForge website is no longer actively maintained. Instead, please follow the link in the profile.
  • BeCPiA  v.86VLSI Vision CPiA kernel driver & mediakit addon (for BeOS 4.5).
  • DICaD  v.1.0DICaD is a free EDA software for VLSI circuits design.
  • SysModLib  v.1.0About The Project: This is a C++ user library built on systemc and systemc-ams libraries intend to develop cycle accurate or non cycle accurate VLSI system models.
  • XSection@KLayout  v.1.0The goal of this project is to provide an add-on to KLayout ( to create and visualize a realistic cross-section view for VLSI designs supporting a wide range of technology options.
  • Async. Simulation and Synthesis Language  v.1.0ASSL (pronounced AY-sil), is a wrapper around CHP, an established async. process description language. This project provides a set of tools that aid the design, simulation, and synthesis of async. VLSI circuits. Common parser, independent tool projects ...
  • ViaDesigner  v.2012.2.1Complete mixed signal electronic circuit schematic capture and simulation software. Combine schematics, SPICE, VHDL, Verilog & VHDL-AMS in a unified design and simulation environment. Powerful and easy-to-use design wizards kick start your design.
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